module pedge_detect (
    input  sys_clk,
    input  rst_n,
    input  sig_i,
    input  detect_en,
    output pedge_o
);

  reg sig_i_d1;
  always @(posedge sys_clk, negedge rst_n) begin
    if (~rst_n) begin
      sig_i_d1 <= 1'b0;
    end else begin
      sig_i_d1 <= sig_i;
    end
  end

  assign pedge_o = (~detect_en) & (sig_i & (~sig_i_d1));

endmodule
